1. Field of the Invention
The present invention relates to a switch circuit device formed of a plurality of field-effect transistors (FETs).
2. Description of the Background Art
For example, GaAs-system switch circuit devices capable of high-speed switching operation are used in transmitter/receiver devices for microwave communication systems. FIG. 9 is a circuit diagram showing an example of a conventional switch circuit device using MESFETs (Metal-Semiconductor Field-Effect Transistors, referred to simply as FETs hereinafter).
The switch circuit device shown in FIG. 9 includes an FET 100 connected between a node Ni connected to a terminal A and a node N3 connected to a terminal B, and an FET 200 connected between a node N2 connected to the terminal A and a node N4 connected to a terminal C. It also includes an FET 300 connected between the node N3 and ground potential and an FET 400 connected between the node N4 and ground potential.
The FETs 100 and 400 have their respective gates connected to a control terminal D through respective resistances and the FETs 200 and 300 have their respective gates connected to a control terminal E through respective resistances. Control voltages V1 and V2 complementary to each other are applied to the control terminals D and E, respectively.
The terminal A is supplied with a high-frequency signal RX0, the terminal B is supplied with a high-frequency signal RX1, and the terminal C is supplied with a high-frequency signal RX2.
FIG. 10 is a diagram showing an example of drain current (Id) versus source-drain voltage (Vds) characteristics of an FET.
For example, when the gate voltage Vgs is 0 V, the drain current Id is about 0.15 A/mm!. When the gate voltage Vgs is deeper than -1.0 V, the drain current Id is approximately zero. Accordingly, for example, the FET turns on when the gate voltage Vgs is 0 V, and it turns off when the gate voltage Vgs is -3.0 V.
In the switch circuit device shown in FIG. 9, for example, when the control voltage V1 is -3.0 V and the control voltage V2 is 0 V, the FETs 200 and 300 turn on and the FETs 100 and 400 turn off. This allows signal transmission between the terminals A and C. These voltages in operation and the states of the FETs are shown in the parentheses.
On the other hand, when the control voltage V1 is 0 V and the control voltage V2 is -3.0 V, the FETs 100 and 400 turn on and the FETs 200 and 300 turn off. This allows signal transmission between the terminals A and B.
In a conventional switch circuit device using FETs, the transmission path is switched by utilizing the linear region with the gate voltage Vgs of 0 V (ON state) in the drain current (Id) versus source-drain voltage (Vds) characteristics and the state with application of the gate voltage Vgs at or below the pinch-off voltage (OFF state).
However, as shown in FIG. 11, a gate voltage Vgs exceeding zero can be applied to the FET until a forward current flows to the gate (in FIG. 11, Vgs=0.5 V). If this state can be utilized as the ON state, it is possible to pass larger current than in the case of Vgs=0 and to reduce the inclination of the linear region (ON resistance Ron), so as to realize high power-handling capability and low insertion loss.
The conventional switch circuit device shown in FIG. 9 requires a negative power-supply circuit because it needs application of negative control voltage to turn on and off the FETs 100, 200, 300, and 400. This hinders size reduction of the switch circuit device.
When the switch circuit device is operated by using positive control voltage, it is necessary to pull up FETs in the switch circuit device with a positive voltage. Methods for pulling up an FET with positive voltage include a method in which an FET is pulled up by using a power-supply voltage and a method in which an FET is pulled up without using a power-supply voltage.
FIG. 12 is a circuit diagram showing a switch circuit device in which FETs are pulled up by using power-supply voltage.
The switch circuit device shown in FIG. 12 includes an FET 1 connected between the nodes N1 and N3, an FET 2 connected between the nodes N2 and N4, an FET 3 connected between the nodes N3 and N5, and an FET 4 connected between the nodes N4 and N5. The FETs 1 and 4 have their respective gates connected to a control terminal D through respective resistances and the FETs 2 and 3 have their respective gates connected to a control terminal E through respective resistances.
The FETs 1 to 4 have the characteristics shown in FIG. 11. The terminal A and the node N5 are connected to a power-supply terminal F through resistances. A power-supply voltage Vdd of +3.0 V is applied to the power-supply terminal F.
For example, when the control voltage V1 is 0 V and the control voltage V2 is +3.0 V, the FETs 2 and 3 turn on and the FETs 1 and 4 turn off. At this time, the nodes N1, N2 and N5 are pulled up to +3.0 V directly from the power-supply terminal F, the node N3 is pulled up to +3.0 V through the FET 3, and the node N4 is pulled up to +3.0 V through the FET 2. These voltages in operation and the states of the FETs are shown in the parentheses.
In this case, however, the gate voltage Vgs at the transistors 2 and 3 in the ON state is 0 V, therefore the gate voltage Vgs cannot be applied positively. Accordingly, a large current cannot be passed through the FETs. That is to say, the FETs 1 to 4 cannot exhibit their capability of allowing application of positive gate voltage Vgs.
FIG. 13 is a circuit diagram showing a switch circuit device in which FETs are pulled up without using power-supply voltage.
In the switch circuit device shown in FIG. 13, too, the FET 1 is connected between the nodes N1 and N3, the FET 2 is connected between the nodes N2 and N4, the FET 3 is connected between the nodes N3 and N5, and the FET 4 is connected between the nodes N4 and N5. The FETs 1 and 4 have their respective gates connected to the control terminal D through respective resistances and the FETs 2 and 3 have their respective gates connected to the control terminal E through respective resistances. These FETs 1 to 4 have the characteristics shown in FIG. 11.
For example, when the control voltage V1 is 0 V and the control voltage V2 is +3.0 V, the FETs 2 and 3 turn on and the FETs 1 and 4 turn off. At this time, the forward current transiently flowing to the FETs 2 and 3 due to the +3.0 V control voltage V2 charges external capacitances C0, C1, C2 and a capacitance 13. Hence, the voltages at the nodes N1, N2, N3, N4 and N5 become lower by the built-in voltage of the FETs down to +2.5 V. These voltages in operation and the states of the FETs are shown in the parentheses.
In this case, a gate voltage Vgs at +0.5 V is applied to the FETs 2 and 3 in the ON state, and a large drain current can be passed. That is to say, the switch circuit device shown in FIG. 13 can effectively utilize the capability of the FETs 1 to 4 of allowing application of a large positive gate voltage Vgs. As a result, the switch circuit device shown in FIG. 13 can provide lower insertion loss than the switch circuit device shown in FIG. 12.
However, the switch circuit device shown in FIG. 13 raises the following problem. The gate voltage Vgs applied to the FETs 1 and 4 in the OFF state is -2.5 V. If the pinch-off voltage Vp of the FETs 1 to 4 is -1.0 V, the difference between the gate voltage Vgs at the OFF-state FETs 1 and 4 and the pinch-off voltage is 1.5 V. The difference between the gate voltage Vgs at an FET in an OFF state and the pinch-off voltage Vp determines the withstand voltage characteristic.
In the switch circuit device shown in FIG. 12, the gate voltage Vgs at the FETs 1, 4 in the OFF state is -3.0 V. In this case, the difference between the gate voltage Vgs at the OFF-state FETs 1, 4 and the pinch-off voltage Vp is 2 V.
This way, in the switch circuit device shown in FIG. 13, FETs in the OFF state present an inferior withstand voltage characteristic to those in the switch circuit device shown in FIG. 12. Hence, it is prone to signal leakage and presents an input/output power characteristic with deteriorated linearity.
FIG. 14 is a circuit diagram showing another example of a conventional switch circuit device. In the switch circuit device shown in FIG. 14, five FETs 11 to 15 are connected in series between the terminals A and B and five FETs 21 to 25 are connected in series between the terminals A and C. The FETs 11 to 15 have their respective gates connected to the control terminal D through respective resistances and the FETs 21 to 25 have their respective gates connected to the control terminal E through respective resistances. Mutually complementary control voltages V1 and V2 are applied to the control terminals D and E.
In the switch circuit device shown in FIG. 14, if the control voltage V1 is +3.0 V and the control voltage V2 is 0 V, the FETs 11 to 15 turn on and the FETs 21 to 25 turn off. This allows signal transmission between the terminals A and B.
In this case, the voltage between the terminals A and C is distributed among the five FETs 21 to 25. Then, when signal is transmitted between the terminals A and B, signal leakage is less liable to occur between the terminals A and C. Further, it is possible to reduce the size of each FET to improve the yield.
However, actually, in the FETs 21 to 25 in the OFF state, the voltage applied between the gate and source of the FET 21 placed on one end and the voltage applied between the gate and drain of the FET 25 placed on the other end are larger than the value in the case of equal distribution. Then, when large power signal is transmitted between the terminals A and B, signal leakage is apt to occur between the terminals A and C.